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[Embeded-SCM DevelopFIFO

Description: 介绍异步FIFO结构的,对搞微电子的有用-Asynchronous FIFO structure introduced on the usefulness of engaging in micro-electronics
Platform: | Size: 545792 | Author: | Hits:

[VHDL-FPGA-Verilogasynchronous-FIFO-structure

Description:
Platform: | Size: 545792 | Author: john | Hits:

[Windows Developsdh

Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
Platform: | Size: 6144 | Author: 韩冰 | Hits:

[OtherAsynchronousFIFOdesign

Description: 异步FIFO的设计,里边讲得很详细! 1.单时钟结构 2.双时钟结构——双钟结构1 3.双时钟结构——双钟结构2 4.双时钟结构——双钟结构3 5.脉冲模式FIFO-Asynchronous FIFO design, very detailed inside! 1. 2 single-clock structure. Dual-clock structure- the structure of dual-bell 1 3. Dual-clock structure- the structure of dual-bell 2 4. Dual-clock structure- the structure of dual-bell 3 5. FIFO burst mode
Platform: | Size: 561152 | Author: mhb | Hits:

[Software Engineeringfifo

Description: 异步fifo的经典讲解,包括亚稳态的产生,同步电路的构造,fifo电路的结构,源代码实现。-Asynchronous fifo on the classic, including the emergence of metastable, the structure of synchronous circuits, fifo circuit structure, the source code to achieve.
Platform: | Size: 3224576 | Author: 王玉 | Hits:

[Software EngineeringFIFO

Description: 翻译的异步FIFO结构的经典文章,通俗易懂,大师级的人物!-Asynchronous FIFO structure of the translation of the classic article, easy to understand, the masters of the people!
Platform: | Size: 545792 | Author: dean | Hits:

[VHDL-FPGA-VerilogAsynchronous-FIFO-structureadesign

Description: 异步FIFO结构和FPGA设计,首先介绍异步FIFO的概念、应用及其结构,然后分析实现异步FIFO的难点问题及其解决办法;在传统设计的基础上提出一种新颖的电路结构并对其进行综合仿真和FPGA实现-The asynchronous FIFO structure and FPGA design, first introduced the asynchronous FIFO concept, application, and its structure, and then analyze the asynchronous FIFO difficult problems and their solutions proposes a novel circuit structure on the basis of traditional design and comprehensive simulation and FPGA implementation
Platform: | Size: 130048 | Author: 杨光 | Hits:

[VHDL-FPGA-Verilogmyuart

Description: 使用verilog语言编写的异步串口模块,带有16级深的FIFO,它与DSP28335的SCI相似,可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas
Platform: | Size: 492544 | Author: 夏小保 | Hits:

[Game Hook CrackAPC

Description: APC中文叫异步过程调用(APC)是NT异步处理体系结构中的一个基础部分。Alertable IO(告警IO)提供了更有效的异步通知形式,当IO请求完成后,一旦线程进入可告警状态,回调函数将会执行,也就是一个APC的过程。线程进入告警状态时,内核将会检查线程的APC队列,如果队列中有APC,将会按FIFO方式依次执行。如果队列为空,线程将会挂起等待事件对象。以后的某个时刻,一旦APC进入队列,线程将会被唤醒执行APC。-APC called asynchronous procedure call (APC) is a basis of NT asynchronous processing system structure. Alertable IO (alarm IO) provides a more effective form of asynchronous notification, when after the completion of the I/o requests, once the thread enters the alarm status, the callback function will be executed, which is a process of APC. Thread into the alarm status, the kernel will check the threads of the APC queue, have the APC, if the queue will be executed in sequence according to the FIFO method. If the queue is empty, the thread will hang wait for event object. Sometime later, once the APC enters the queue, the thread will be awakened APC execution.
Platform: | Size: 14336 | Author: mrbang | Hits:

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